Every programmable controller is built around a scan cycle: read inputs, execute the user program, write outputs, repeat endlessly while the 24 V supply is present. Most of that working memory is fast volatile SRAM, which loses its contents the instant power is removed - and yet a production line expects its counters, latch relays, recipe values and running clock to survive the night switch-off, a brown-out or a mains dip, and a machine tool expects its parameters, tool offsets and axis zero-reference positions to survive as well. Retention is therefore not an optional feature but a defined subsystem with its own load profile and its own failure economics. This first paper on nickel-metal hydride retention for PLCs and CNC controls explains exactly what must be remembered and why, and dissects the very low-current load that keeps CMOS SRAM and a real-time clock alive when the main supply is gone. Real controllers anchor the discussion: one small PLC family offers either RAM plus a capacitor for about two weeks of retention at 25 degrees C or RAM plus a battery for about five years; a widely used compact PLC relies on an internal supercapacitor for roughly 50 to 100 hours of clock retention and an optional battery card for up to 200 days; a high-end CPU quotes a backup time around six weeks at 40 degrees C and retentive data areas measured in megabytes; and CNC controls have long used 3.6 V primary-lithium cells, some with only a five-minute hot-swap window. These figures frame the three retention architectures - capacitor, battery and fully non-volatile memory - whose selection and design the second paper addresses.
During operation the CPU executes the user program - written to the IEC 61131-3 languages in a PLC - from working memory, updating input/output images, internal flags, timers, counters and data registers on every scan. Fast SRAM is preferred for this because it has unlimited endurance and fast write timing, but it is volatile: remove the supply and its bits decay within milliseconds. Program code is usually mirrored in flash, but the live state of the machine - accumulated counts, partial batches, setpoints entered by the operator - exists only in that volatile store.
Controllers therefore designate retentive (latch) ranges whose contents must survive power loss, distinct from non-retentive tags that are allowed to reset. A modern modular CPU may retain several megabytes of such data; the designer marks which tags are retentive and the hardware must keep precisely those cells, and the real-time clock, alive across the outage.
The real-time clock (RTC) keeps timestamps, event logs, scheduled routines and shift counters correct through power-off. It is a tiny circuit - board designs use dedicated RTC chips such as the DS3231 or PCF2129 with a backup input - but it runs continuously and its accuracy is specified independently, commonly within a few tens of seconds per month at 25 degrees C (one compact PLC quotes plus or minus 90 seconds per month, a modular family around 27).
Because the RTC never stops, its microampere draw is integrated over the entire powered-off interval and frequently dominates the retention energy budget alongside SRAM standby current. A source that can hold large SRAM for days but cannot also keep the oscillator running still fails the application, which is why retention sizing always sums SRAM standby, RTC and any supervisory circuitry rather than counting memory alone.
A CNC control raises the stakes. Beyond the ladder program it stores system parameters, servo tuning, tool geometry and wear offsets, pitch-error compensation and, for axes with absolute encoders, the machine's zero-return reference positions. Losing this battery-backed memory means re-entering parameters and re-homing every axis - hours of skilled downtime and a risk of a crash if an offset is restored incorrectly. This is why CNC maintenance schedules treat the memory battery as a critical service part.
Popular controls use primary-lithium packs - a 3.6 V, 1,750 mAh cell or a 6 V twin pack are common service items - and several specify a short, minutes-long window in which the exhausted cell must be exchanged while the control is still powered, before the CMOS memory decays. That hot-swap constraint is a direct consequence of having no independent energy reservoir in the retention design.
Industry retains volatile memory three ways. A capacitor or supercapacitor stores enough charge for the SRAM and RTC over short outages - a small PLC obtains about two weeks from a capacitor, a compact controller around 50 to 100 hours of clock from an internal supercapacitor charged during running - with the advantage of essentially unlimited cycle life and no service part, but the disadvantage of a horizon measured in days that shrinks at high temperature. A primary or rechargeable battery extends retention to months or years. The third route removes volatile memory altogether, using flash, FRAM or MRAM so that latch data is intrinsically non-volatile; one modern modular PLC family advertises a battery-less CPU on exactly this basis, and a compact series holds its clock for ten days from a large capacitor charged in the first thirty minutes of running.
The first animated figure layers the data a controller must retain; the second compares, qualitatively, how the three architectures preserve that data as off-power time grows from minutes to years, showing the crossover points a designer must design around.
Retention has two electrical phases. At the instant of failure a supervisor - a voltage detector and watchdog in the class of a TPS3823 or MAX6369 - detects the collapsing rail, asserts a non-maskable warning and gives the CPU a brief hold-up interval, often from a capacitor, to finish the scan and flush critical registers into the retained domain. After that, only the microampere-level standby load of retained SRAM and the RTC remains, sustained for the long outage by the retention source.
This split - a short, higher-current orderly-save phase and a very long, ultra-low-current retention phase - dictates source selection. A capacitor excels at the first but cannot span months; a battery spans the long tail but must be switched in cleanly and monitored; non-volatile memory handles persistence but flash has finite write endurance, which one PLC family quantifies at roughly 100,000 updates, making it less suited to data rewritten on every scan.
The analysis produces a clear specification: a source that sustains the summed SRAM-standby and RTC microampere load for the target powered-off interval at worst-case temperature; a short hold-up reservoir for the orderly power-fail save; a clean switchover that never interrupts the retention rail; predictable service life with a monitoring or replacement strategy; and, for CNC, support for safe battery exchange without losing memory. The second paper turns this into a concrete retention design and compares rechargeable nickel-metal hydride honestly with supercapacitors, primary lithium and fully non-volatile memory; the third maps the IEC 61131-2, EMC, environmental and battery-standard evidence behind a compliant controller.
Recognising retention as a two-phase, microampere-dominated subsystem is the mindset that separates a controller that powers back up into the correct state, with the right time and the correct axis positions, from one that greets the operator with a cleared memory and a lost shift of production.
Weijiang Power designs and manufactures sealed nickel-metal hydride cells and matched industrial packs for remote, off-grid and safety-related equipment, and supports OEM partners with IEC 61951-2 performance files, IEC 62133-2 safety evidence, pulse-load characterisation, wide-temperature testing and charger/pack co-validation. Tell us your duty cycle, peak current, temperature envelope, autonomy target and the standards your product must meet, and our engineers will specify a cell-and-pack combination that protects runtime, reliability and service life. Review the range on the products page.
